This application claims the benefit of Korean Application No. 97-56081 filed Oct. 29, 1997, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a device for a data communication, and more particularly, to a data transmission device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving data transmission efficiency without increasing a clock speed of devices.
2.Discussion of the Related Art
For a data transmission, binary data comprising a low level data and a high level data are transmitted at data levels of 0 V (low level)xcx9c5 V (high level). Since a clock signal determines an operation speed of computer, computer designers have made an effort to improve the operation speed of computer having a faster clock signal. Consequently, a logic of a CMOS transistor takes an important role in developing a faster data processing system. Operation of the CMOS transistor depends on a turn-on voltage of the device, which is a threshold voltage.
A data transmission device according to a background art will be described with reference to the accompanying drawings.
FIG. 1 is a circuit diagram illustrating a CMOS transistor according to the background art. As shown in FIG. 1, when an input voltage Vin is greater than Vtp+VDD (Vtp less than 0), a PMOS PM is turned off and an NMOS NM is thus saturated. Vtp represents a threshold voltage of the PMOS PM. An output voltage becomes a ground voltage Vss because only the NMOS NM is turned on.
Conversely, when the input voltage Vin is smaller than the threshold voltage Vtn, the NMOS NM is turned off and the PMOS PM is saturated. As a result, only the PMOS PM is turned on. Therefore, the output voltage becomes a power source voltage, VDD.
Both the PMOS PM and NMOS NM are in a non-saturated state when the input voltage Vin is greater than the threshold voltage Vtn of the NMOS NM and smaller than Vtp+VDD. The voltage is determined at the position where a current of the PMOS PM becomes identical to that of the NMOS NM.
Consequently, when the input voltage is a high level, the output voltage becomes a low level. In contrast, when the input voltage is a low level, the output becomes a high level. As a result, only a binary data transmission is possible in the background art.
Another background art is disclosed in the U.S. Pat. No. 5,539,333 as shown in FIG. 2, which illustrates a circuit diagram of a low voltage differential clock signal (LVDS) having a driver circuit connected with a receiver circuit. The driver circuit inputs differential clock signals IN1 and IN2 and processes the signals for transmitting to the receiver circuit.
The driver circuit converts the differential clock signals IN1 and IN2 to low voltage differential signals. The signals are thus used in the other circuits of the data processing system, thereby transmitting the low voltage differential signals to the receiver circuit through output terminals OUT1 and OUT2. Both the driver circuit and the receiver circuit are realized by a CMOS technology.
A resistor RT of the receiver circuit is for matching a capacitance with an inductance of a transmission line 2 between the driver circuit and the receiver circuit.
The receiver circuit receives the low voltage differential signals from the driver circuit and converts the signals to the various frequencies to be used in the other circuits (not shown).
The conventional data transmission device generates a delay time by means of xcfx84RC when a voltage difference between transmission lines is large enough during the data transmission, whereas it restores a data by a differential amplifier using the voltage difference.
FIG. 3 is a waveform of two transmission data of FIG. 2. A signal having an 1 V difference with reference to 1.1 V is transmitted as shown in FIG. 3.
FIG. 4 is a block diagram illustrating a liquid crystal display (LCD) device adopting a data transmission device including a background art CMOS transistors. As shown in FIG. 4, the LCD device includes an LCD panel 41, a plurality of source drivers 43, a plurality of gate drivers 45, and an LCD controller 47. The source drivers 43 and the gate drivers 45 are disposed around the LCD panel 41. The LCD controller 47 controls the source drivers 43 and the gate drivers 45.
In the background art LCD device, the LCD controller 47 transmits a control signal to the gate drivers 45 and respective 6 or 8 bit data per each of R, G, B image signals to the source drivers 43. Therefore, when the 6 bit data is transmitted, total 18 bit data are outputted to the source drivers 43. Total 24 bit data are transmitted to the source drivers 43 in case that the 8 bit data is transmitted.
R, G, B data in two channels must be transmitted simultaneously as a resolution increases. As a result, 36 transmission lines to 48 transmission lines are required to transmit R, G, B data to the source drivers 43.
The aforementioned background art data transmission devices using in the LCD device have several problems as follows.
With an increased data transmission speed using the CMOS, increase in both a power consumption and an electromagnetic interference (EMI) is unavoidable.
Especially in LVDS, two transmission lines are required for a data transmission. Thus, to improve a transmission efficiency, the data transmission device must have a speed faster than a clock speed of a conventional CMOS. Further, there is no compatibility with any other conventional CMOS interface. Since a clock signal having a fast speed is required to receive a fast signal, a phase lock loop (PLL) is additionally required, thereby complicating a circuit configuration.
Accordingly, the present invention is directed to a data transmission device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a data transmission device for a liquid crystal display device which improves a data transmission efficiency by converting a binary data to a ternary data.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a data transmission device according to the present invention includes a decoder for converting a binary data to a ternary data, a ternary data generator for generating three logic levels corresponding to a power source voltage, a ground voltage, and an intermediate voltage between the power source voltage and the ground voltage, a data detector for converting the three logic levels from the ternary data generator to pairs of binary data, and an encoder for restoring the pairs of binary data to binary data.
In another aspect of the present invention, a data transmission device includes a decoder converting a first binary data to a ternary data, a ternary data generator coupled to the decoder and generating three logic levels corresponding to a power source voltage, an intermediate voltage, and a ground voltage, the intermediate voltage having a voltage level between the power source voltage and the ground voltage, a ternary data detector coupled to the ternary data generator and converting the three logic levels from the ternary data generator to pairs of second binary data, and an encoder coupled to the data detector and restoring the pairs of second binary data to the first binary data.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.